SAT Technology
Why SAT Inspection Mattersin the Era of Stacked Semiconductors
As semiconductors stack dies in layers like HBM, gather several dies into one package like chiplets, and bond chips onto thick metal and ceramic substrates like power modules, the defects that decide yield and reliability have moved from the surface to bonded interfaces that no camera can see. Voids, delamination and cracks at these interfaces are often air gaps thinner than 1 µm. The method that finds such air gaps most clearly without cutting the sample is scanning acoustic tomography (SAT, also known as SAM or C-SAM). This page explains why SAT has become a required process inspection rather than an option. Terminology, physics and frequency selection are covered in the SAT Technology Guide; what makes MIT systems different is covered in Why MIT SAT.
1. Defects have moved from the surface to the bonded interface
In planar devices most failures showed at the surface and were caught by optical inspection (AOI) and electrical test. With stacking and heterogeneous integration now standard, the number of bonded interfaces between die and die, die and interposer, chip and substrate, substrate and baseplate has multiplied. Each is a boundary between materials with different thermal expansion, so stress, moisture and process variation concentrate there. The place where defects form has changed.
| Structure | Critical interface | Typical defects | What happens if missed |
|---|---|---|---|
| HBM and stacked memory | Micro-bumps and hybrid-bond interfaces between dies | Non-wet joints, micro-voids, unfilled underfill | One bad die scraps the whole stack; higher thermal resistance |
| 2.5D/3D and chiplet packages | Die to interposer, interposer to substrate, die to mold | Delamination, bump cracks, underfill voids | Failures after reliability testing; field returns |
| Wafer bonding (W2W, D2W) | Bond interface | Voids, particle-induced non-bonding | Die loss during thinning and later steps |
| Power modules | Solder and sintered layers between chip and DCB/AMB substrate; substrate to baseplate | Voids, delamination, cracks in sintered layers | Higher thermal resistance, overheating, shorter life |
| Substrates, MLCC and other components | Interlayer bonds | Interlayer delamination, cracks | Moisture ingress, electrical failure |
These cases share three traits. The defect sits tens of micrometres to several millimetres below opaque material such as silicon, metal or mold compound; it is often sub-micron thick; and it typically looks electrically normal at first, then grows under thermal cycling and moisture into a failure.
2. Why other inspection methods are not enough on their own
Each method responds to a different physical quantity, so each has a different sensitivity to interface defects.
| Method | What it senses | Good at | Tends to miss |
|---|---|---|---|
| Optical inspection (AOI) | Reflected light from the surface | Surface particles, scratches, bump shape | Anything under opaque material |
| X-ray (2D and CT) | Transmission governed by density differences | Solder voids, wiring and bump geometry, bridging | Thin delamination (almost no density contrast), non-bonds between like materials |
| Infrared (IR) | Light transmitted through silicon | Voids at wafer-bond interfaces | Defects behind metal or mold; structures containing metal layers |
| Electrical test | Electrical characteristics | Opens, shorts, functional failures | Latent defects that are still electrically normal (partial delamination, voids) |
| Ultrasonic inspection (SAT) | Change in acoustic impedance at interfaces | Delamination, voids, cracks, non-wets, with depth resolved | Precise geometry and dimensional measurement |
The key point is that delamination must be detected by whether it exists, not by how thick it is. X-ray sees density contrast along the beam path, so a delamination with almost no thickness does not appear. Ultrasound is almost totally reflected at a solid-to-air boundary and the echo flips phase, so an air gap of sub-micron thickness still produces a clear signal. IPC/JEDEC J-STD-035 is the standard procedure for acoustic microscopy of plastic-encapsulated components, and it is used to check for delamination before and after moisture-sensitivity testing.
These methods divide the work rather than compete: X-ray for geometry and wiring, AOI for surfaces, SAT for interfaces, and electrical test for final function. Section 8 of the SAT Technology Guide has a fuller comparison.
3. Why ultrasound is so sensitive to interface defects
- Pulse-echo: a focused transducer sends a short pulse and receives the echoes returning from each boundary. Echo strength is set by the difference in acoustic impedance between the materials on either side.
- Total reflection at air: at a solid-to-air boundary almost 100 percent of the ultrasound is reflected and the phase inverts. Voids and delamination are air gaps, so they return a stronger and more distinctive signal than any other interface.
- Depth selection: echo return time is proportional to depth, so a time gate selects a single interface for imaging (C-scan). In a stack each layer can be imaged separately, which shows directly which interface is at fault.
- Non-destructive: the sample is not cut, so inspected parts move on to the next step and the same part can be compared before and after a process.
Principles, imaging modes and frequency selection are explained in sections 2 and 3 of the SAT Technology Guide.
4. From sampling to 100 percent: why in-line automated SAT
The acoustic microscope was a laboratory instrument for decades, used to read a handful of samples after reliability testing. Three changes have pulled inspection into the line and toward 100 percent coverage.
- The value of the stack: when dies are stacked 8, 12 or 16 high as in HBM, a single bad interface at the last step scraps several known-good dies together. The later a defect is found, the larger the loss, so checking each interface right after bonding is the economical choice.
- Reliability is safety: in power modules, voids in solder and sintered layers raise thermal resistance, and thermal resistance sets lifetime. Automotive and industrial customers increasingly ask for 100 percent inspection data rather than sample results.
- Process feedback: interface defects are the outcome of bonding pressure, temperature, flux and sintering profiles. Returning defect positions and distributions to the process as coordinate data changes the speed of yield learning, and manually read samples cannot close that loop.
Inspecting every part inside the line changes what the equipment must do: automatic loading and alignment of wafers or trays, judgment and sorting without an operator, throughput, repeatable judgment against one criterion, factory integration (SECS/GEM), water management for moisture-sensitive processes, and compensation for warped, thin parts. The difference between laboratory and fully automated in-line systems is summarised in section 6 of the guide.
| Process step | Inspection point | What is checked |
|---|---|---|
| Wafer bonding | Right after bonding, before thinning | Voids and non-bonds at the bond interface |
| Die stacking (TCB, hybrid bonding) | After each stacking step or after the full stack | Non-wet bumps, underfill voids |
| Package assembly | After molding and reflow | Die-to-mold and die-to-substrate delamination, cracks |
| Power-module assembly | After die attach and substrate bonding | Voids in solder and sintered layers, substrate delamination |
| Reliability testing | Before and after MSL and temperature-cycling tests | Onset and growth of delamination (J-STD-035) |
5. What to check before adopting a system
Reviewing these points together with your sample conditions makes comparisons between systems fair.
- Depth and layer structure of the target: the interface you need to see sets the transducer frequency band and the gate settings.
- Conditions for throughput comparison: throughput depends on scan pitch, number of probes and number of inspection zones, so compare at the same pitch on the same sample.
- Warpage range: thin wafers and substrates are warped; check that the system tracks height in real time.
- Water contact: immersion, or a non-immersion method that minimises water contact, and how parts are dried afterwards.
- Accuracy of defect coordinates: automatic judgment, review, binning and process feedback all assume exact x-y coordinates.
- Line integration and criteria management: SECS/GEM integration, version control of judgment criteria, and the format of result data.
How the MIT SFSAT series meets these requirements is shown in the model comparison on the product page and in Why MIT SAT.
Frequently Asked Questions
- Why is delamination inspected with SAT rather than X-ray?
- X-ray images differences in density along the transmission path, so a delamination with almost no thickness barely shows up. Ultrasound is almost totally reflected at any solid-to-air boundary and the echo flips phase, so even a sub-micron air gap gives a clear, distinctive signal. IPC/JEDEC J-STD-035 is the standard procedure for inspecting such delamination by acoustic microscopy. X-ray remains the better tool for wiring and bump geometry; the two methods complement each other.
- Is SAT really necessary for stacked memory such as HBM?
- The defects that decide stacked-memory yield are non-wet joints, micro-voids and unfilled underfill at the bond interfaces between dies, and those interfaces sit under silicon where optical inspection cannot see. Ultrasound can image each interface separately by time gating, so it shows which layer is at fault, and because a single bad interface scraps every good die already in the stack, inspection right after bonding pays for itself.
- Why are power modules inspected with ultrasound?
- Voids and delamination in the solder and sintered layers between chip, substrate and baseplate raise thermal resistance, which leads to overheating and shorter life. These joints lie under thick metal and ceramic, and ultrasound is the practical way to image the whole joint area non-destructively. The same principle applies from the DCB and AMB substrate stage to the assembled module.
- Why use SAT instead of infrared (IR) for wafer-bonding inspection?
- IR passes through silicon and quickly shows voids at silicon-to-silicon bond interfaces, but it is blind wherever a metal layer or an opaque material is in the way. SAT images the interface regardless of optical transparency and resolves defect depth, so metal bonding, hybrid bonding and bonding of dissimilar materials can be inspected on the same system. Many lines use both methods.
- Is sample inspection not enough? Why inspect 100 percent?
- Sampling works once a process is stable and can be managed statistically. In stacked structures, however, one bad interface multiplies into the loss of several dies, and for products such as power modules, where reliability means safety, customers increasingly require 100 percent inspection data. Defect coordinates and distributions from full inspection also feed straight back into process tuning, which turns inspection from a cost into a yield tool.
- At which process steps is SAT inspection performed?
- Typically right after wafer bonding, after each die-stacking step or after the stack is complete, after molding and reflow in package assembly, after die attach and substrate bonding in power-module assembly, and before and after reliability tests such as moisture-sensitivity and temperature cycling. A good rule is that the inspection point comes immediately after any step that creates a new interface.